Hardware Description Languages (HDLs) provide a high-level approach for creating hardware designs. Designs may be as simple as a counter circuit, for example, or as complex as processors and input/output subsystems. The process of event-driven HDL simulation is a way to verify that an HDL-based design will work correctly when implemented in hardware. In order to simulate an HDL design, a model is created for the selected HDL simulator.
One of the more popular HDL languages is System Verilog. Block Statements are one of the key building blocks which comprise the System Verilog language. A block statement provides a means of grouping statements together so that those statements act semantically like a single statement. There are two types of blocks in the System Verilog HDL: sequential blocks, also called begin-end blocks, and parallel blocks, also called fork-join blocks. A parallel block is delimited by the keywords fork and join, fork and join_none, or fork and join_any. The procedural sub-statements in the parallel block are executed concurrently, and the join statement will suspend execution of sequential statements following the block until all sub-statements within the block have completed. If a sub-statement requires more time to complete than the other sub-statements, the join statement will not proceed until the longer statement has completed.
Example 1, shown below, contains an example HDL code segment of a fork-join block and the output resulting from simulation of this HDL code.
CODE:     module m( );     initial     begin: parent_process       #1; $display($time, “ parent_process_start”);       fork        begin: forked_process_1 //Stmt 1          #1; $display($time, “ forked_process_1”);        end        begin: forked_process_2 //Stmt 2          #1; $display($time, “ forked_process_2”);        end       join       #1; $display($time, “ parent_process_end”);     end     endmoduleOUTPUT:       1 parent_process_start       2 forked_process_1       2 forked_process_2       3 parent_process_end